C11

CURS PDN

Introducere in VERILOG

Agenda

Ce este Verilog?

Istoria Verilog

Terminologia Verilog HDL

Modelarea Comportamentului

Modelarea Structurala

Terminologie

Sinteza RTL

Fluxurile tipice pentru sinteza sisimularea RTL

Structura de modelare de bazaVerilog

Un model Verilog HDL (exemplu)

Declararea modulului si a porturilor

Declararea modulului/porturilor in Verilog-2001 si versiunile superioare

Tipuri de date

Tipul de date Net

Variabile

Instantierea Modulelor

Conectarea porturilor

Reguli de conectare a porturilor

Parametri

Asignarea de valori - numere

Numere

Operatori aritmetici

Operatori la nivel de bit

Operatori de reducere

Operatori relationali

Operatori de egalitate

Operatori logici

Operatori de deplasare

Alti operatori

Precedenta operatorilor

Asignare continua

Blocuri de asignare procedurala

Blocul Initial

Blocul always

Blocul always - exemplu

Doua tipuri de asignari procedurale

Asignari cu blocare vs fara blocare

Reguli de utilizare

Doua tipuri de procese RTL

Declaratii/ instructiunicomportamentale

Instructiunea if-else

Instructiunea case

Doua alte forme ale lui case

Buclele forever si repeat

Bucla while

Bucla for

Sincron vs asincron

Clock enable

Counter functional

Functii si task-uri

Definirea unei functii - multiplicator

Invocarea unei functii - MAC

Exemplu de task

Functii vs task-uri

Exemple Verilog

Codificator implementat cu if

module encoder_using_if(binary_out , // 4 bit binary output

encoder_in , // 16-bit input

enable // Enable for the encoder);

//-----------Output Ports---------------output [3:0] binary_out ;

//-----------Input Ports---------------

input enable ; input [15:0] encoder_in ;

//------------Internal Variables--------reg [3:0] binary_out ;

//-------------Code Start-----------------always @ (enable or encoder_in)

begin

binary_out = 0; if (enable) begin

if (encoder_in == 16'h0002) beginbinary_out = 1;

end if (encoder_in == 16'h0004) begin

binary_out = 2; end if (encoder_in == 16'h0008) begin



binary_out = 5;

end if (encoder_in == 16'h0040) begin binary_out = 6;


binary_out = 7;


binary_out = 8;




binary_out = 11;

end if (encoder_in == 16'h1000) beginbinary_out = 12;

end if (encoder_in == 16'h2000) begin binary_out = 13;



binary_out = 15; end

endend

endmodule

Codificator implementat cu case

module encoder_using_case(

binary_out , // 4 bit binary Output

encoder_in , // 16-bit Input

enable // Enable for the encoder

);

output [3:0] binary_out ;

input enable ;

input [15:0] encoder_in ;

reg [3:0] binary_out ;

always @ (enable or encoder_in)

begin

binary_out = 0;

if (enable) begin

case (encoder_in)

16'h0002 : binary_out = 1;

16'h0004 : binary_out = 2;

16'h0008 : binary_out = 3;

16'h0010 : binary_out = 4;

16'h0020 : binary_out = 5;

16'h0040 : binary_out = 6;

16'h0080 : binary_out = 7;

16'h0100 : binary_out = 8;

16'h0200 : binary_out = 9;

16'h0400 : binary_out = 10;

16'h0800 : binary_out = 11;

16'h1000 : binary_out = 12;

16'h2000 : binary_out = 13;

16'h4000 : binary_out = 14;

16'h8000 : binary_out = 15;

endcase

end

end

endmodule

Codificator cu prioritate folosind if-else

module pri_encoder_using_if (binary_out , // 4 bit binary output

encoder_in , // 16-bit input enable // Enable for the encoder);

output [3:0] binary_out ;input enable ;


reg [3:0] binary_out ;

always @ (enable or encoder_in)

beginbinary_out = 0;

if (enable) beginif (encoder_in == {{14{1'bx}},1'b1,{1{1'b0}}}) beginbinary_out = 1;

end else if (encoder_in == {{13{1'bx}},1'b1,{2{1'b0}}}) beginbinary_out = 2;



end else if (encoder_in == {{10{1'bx}},1'b1,{5{1'b0}}}) begin

binary_out = 5; end else if (encoder_in == {{9{1'bx}},1'b1,{6{1'b0}}}) begin

binary_out = 6; end else if (encoder_in == {{8{1'bx}},1'b1,{7{1'b0}}}) begin binary_out = 7;

end else if (encoder_in == {{7{1'bx}},1'b1,{8{1'b0}}}) begin binary_out = 8;

end else if (encoder_in == {{6{1'bx}},1'b1,{9{1'b0}}}) begin binary_out = 9;

end else if (encoder_in == {{5{1'bx}},1'b1,{10{1'b0}}}) beginbinary_out = 10; end else if (encoder_in == {{4{1'bx}},1'b1,{11{1'b0}}}) begin

binary_out = 11; end else if (encoder_in == {{3{1'bx}},1'b1,{12{1'b0}}}) begin

binary_out = 12; end else if (encoder_in == {{2{1'bx}},1'b1,{13{1'b0}}}) beginbinary_out = 13;


end else if (encoder_in == {1'b1,{15{1'b0}}}) begin binary_out = 15;

endend

end

endmodule

Codificator implementat cu assign

module pri_encoder_using_assign (

binary_out , // 4 bit binary output

encoder_in , // 16-bit input

enable // Enable for the encoder

);

output [3:0] binary_out ;

input enable ;


wire [3:0] binary_out ;

assign binary_out = (!enable) ? 0 : (

(encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 :

(encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 :

(encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 :

(encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 :

(encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 :

(encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 :

(encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 :

(encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 :

(encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 :

(encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 :

(encoder_in == 16'bxxxx_x100_0000_0000) ? 10 :

(encoder_in == 16'bxxxx_1000_0000_0000) ? 11 :

(encoder_in == 16'bxxx1_0000_0000_0000) ? 12 :

(encoder_in == 16'bxx10_0000_0000_0000) ? 13 :

(encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);

endmodule

Decodificator implementat cu case

module decoder_using_case (

binary_in , // 4 bit binary input

decoder_out , // 16-bit out

enable // Enable for the decoder

);

input [3:0] binary_in ;

input enable ;

output [15:0] decoder_out ;

reg [15:0] decoder_out ;

always @ (enable or binary_in)

begin

decoder_out = 0;

if (enable) begin

case (binary_in)

4'h0 : decoder_out = 16'h0001;










4'hA : decoder_out = 16'h0400;

4'hB : decoder_out = 16'h0800;

4'hC : decoder_out = 16'h1000;

4'hD : decoder_out = 16'h2000;

4'hE : decoder_out = 16'h4000;

4'hF : decoder_out = 16'h8000;

endcase

end

end

endmodule

Decodificator implementat cu assign

module decoder_using_assign (binary_in , // 4 bit binary inputdecoder_out , // 16-bit out enable // Enable for the decoder);input [3:0] binary_in ;input enable ; output [15:0] decoder_out ;

wire [15:0] decoder_out ; assign decoder_out = (enable) ? (1

Multiplexor implementat cu assign

module mux_using_assign(

din_0 , // Mux first input

din_1 , // Mux Second input

sel , // Select input

mux_out // Mux output

);

//-----------Input Ports---------------

input din_0, din_1, sel ;

//-----------Output Ports---------------

output mux_out;

//------------Internal Variables--------

wire mux_out;

//-------------Code Start-----------------

assign mux_out = (sel) ? din_1 : din_0;

endmodule //End Of Module mux

Multiplexor implementat cu if

module mux_using_if(

din_0 , // Mux first input

din_1 , // Mux Second inputsel , // Select input

mux_out // Mux output

);

//-----------Input Ports---------------

input din_0, din_1, sel ;//-----------Output Ports---------------

output mux_out;


reg mux_out;

//-------------Code Starts Here---------always @ (sel or din_0 or din_1)

begin : MUX

if (sel == 1'b0) begin

mux_out = din_0;

end else beginmux_out = din_1 ;

end

end

endmodule //End Of Module mux

Multiplexor implementat cu case

module mux_using_case(din_0 , // Mux first inputdin_1 , // Mux Second inputsel , // Select inputmux_out // Mux output);//-----------Input Ports---------------input din_0, din_1, sel ;//-----------Output Ports---------------output mux_out;//------------Internal Variables--------reg mux_out;//-------------Code Starts Here---------always @ (sel or din_0 or din_1)begin : MUXcase(sel )

1'b0 : mux_out = din_0;1'b1 : mux_out = din_1;

endcase endendmodule //End Of Module mux

Bistabil D cu reset asincron

module dff_async_reset (data , // Data Inputclk , // Clock Inputreset , // Reset input q // Q output);//-----------Input Ports---------------input data, clk, reset ; //-----------Output Ports---------------output q;//------------Internal Variables--------reg q;//-------------Code Starts Here---------always @ ( posedge clk or negedge reset)if (~reset) beginq

Bistabil D cu reset sincron

module dff_sync_reset (data , // Data Inputclk , // Clock Inputreset , // Reset inputq // Q output);//-----------Input Ports---------------input data, clk, reset ; //-----------Output Ports---------------output q;//------------Internal Variables--------reg q;//-------------Code Starts Here---------always @ ( posedge clk)if (~reset) beginq

Bistabil T cu reset asincron

module tff_async_reset (data , // Data Inputclk , // Clock Inputreset , // Reset inputq // Q output);//-----------Input Ports---------------input data, clk, reset ; //-----------Output Ports---------------output q;//------------Internal Variables--------reg q;//-------------Code Starts Here---------always @ ( posedge clk or negedge reset)if (~reset) beginq

Bistabil T cu reset sincron

module tff_sync_reset (data , // Data Inputclk , // Clock Inputreset , // Reset inputq // Q output);//-----------Input Ports---------------input data, clk, reset ; //-----------Output Ports---------------output q;//------------Internal Variables--------reg q;//-------------Code Starts Here---------always @ ( posedge clk)if (~reset) beginq

Latch D

module dlatch_reset (data , // Data Inputen , // LatchInputreset , // Reset inputq // Q output);//-----------Input Ports---------------input data, en, reset ; //-----------Output Ports---------------output q;//------------Internal Variables--------reg q;//-------------Code Starts Here---------always @ ( en or reset or data)if (~reset) beginq

Numarator crescator pe 8 biti

module up_counter (out , // Output of the counterenable , // enable for counterclk , // clock Inputreset // reset Input);//----------Output Ports--------------

output [7:0] out;//------------Input Ports--------------

input enable, clk, reset;//------------Internal Variables--------

reg [7:0] out;//-------------Code Starts Here-------always @(posedge clk)if (reset) beginout

Numarator descrescator pe 8 biti

module up_down_counter (

out , // Output of the counter

up_down , // up_down control for counterclk , // clock input

reset // reset input

);

//----------Output Ports--------------

output [7:0] out;//------------Input Ports--------------

input [7:0] data;

input up_down, clk, reset;


reg [7:0] out;//-------------Code Starts Here-------

always @(posedge clk)

if (reset) begin // active high reset

out

Numarator Gray

module gray_counter (

out , // counter out

enable , // enable for counter

clk , // clockrst // active hight reset

);

//------------Input Ports--------------

input clk, rst, enable; //----------Output Ports----------------

output [ 7:0] out;


wire [7:0] out;

reg [7:0] count;//-------------Code Starts Here---------

always @ (posedge clk)

if (rst)

count

Calcul paritate folosind assign

module parity_using_assign (data_in , // 8 bit data inparity_out // 1 bit parity out);output parity_out ;input [7:0] data_in ;

wire parity_out ;

assign parity_out = (data_in[0] ^ data_in[1]) ^ (data_in[2] ^ data_in[3]) ^ (data_in[4] ^ data_in[5]) ^ (data_in[6] ^ data_in[7]);

endmodule

Calcul paritate folosind functii -v1

module parity_using_function (data_in , // 8 bit data inparity_out // 1 bit parity out);output parity_out ;input [7:0] data_in ;

wire parity_out ; function parity;

input [31:0] data; beginparity = (data_in[0] ^ data_in[1]) ^

(data_in[2] ^ data_in[3]) ^ (data_in[4] ^ data_in[5]) ^ (data_in[6] ^ data_in[7]);

end endfunction

assign parity_out = parity(data_in);endmodule

Calcul paritate folosind functii -v2

module parity_using_function2 (data_in , // 8 bit data inparity_out // 1 bit parity out);output parity_out ;input [7:0] data_in ;

wire parity_out ;function parity;

input [31:0] data; integer i; begin parity = 0; for (i = 0; i < 32; i = i + 1) begin parity = parity ^ data[i];

end end

endfunction always @ (data_in)beginparity_out = parity(data_in);

endendmodule

Calcul paritate simplificat

module parity_using_bitwise (

data_in , // 8 bit data in

parity_out // 1 bit parity out

);

output parity_out ;

input [7:0] data_in ;

assign parity_out = ^data_in;

endmodule

Semisumator folosind porti

module half_adder_gates(x,y,sum,carry);

input x,y;

output sum,carry;

and U_carry (carry,x,y);

xor U_sum (sum,x,y);

endmodule

Sumator folosind porti

module full_adder_gates(x,y,z,sum,carry);

input x,y,z;

output sum,carry;

wire and1,and2,and3,sum1;

and U_and1 (and1,x,y),

U_and2 (and2,x,z),

U_and3 (and3,y,z);

or U_or (carry,and1,and2,and3);

xor U_sum (sum,x,y,z);

endmodule

Sumator/scazator pe 8 biti

module addsub(

input [7:0] dataa,

input [7:0] datab,

input add_sub, // if this is 1, add; else subtract

input clk,

output reg [8:0] result);

always @ (posedge clk)

begin

if (add_sub)

result

Date post:	18-Nov-2015
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