Computer
Architecture
Cătălina Mancaș Dan Mancaș
[email protected] [email protected]
Universitatea din Craiova
Facultatea de Automatică, Calculatoare și Electronică
Catedra de Ingineria Calculatoarelor și Comunicații
Basic Concepts
The structure of a computer
Way of functioning
COMPUTER ARCHITECTURE – The 5-Unit Structure
Overview
The Digital Computer. Definitions; Features.
Computing Systems Study;
Introducing Computer Architecture;
The Stored Program Concept;
The von Neumann Principles;
The von Neumann Model: the 5-unit structure;
The Instruction Cycle.
2
COMPUTER ARCHITECTURE – The 5-Unit Structure
The Digital Computer
A digital computer is a complex equipment containing millions of elementary electronic components.
A hierarchical system: several interrelated subsystems - lowest level of elementary subsystems: components.
Unique definition: impossible;
Several (from different points of view).
3
COMPUTER ARCHITECTURE – The 5-Unit Structure
The Digital Computer. Definitions.
Definition #1:
A digital computer is a system intended to automate computations on discrete information in accordance with given algorithms.
4
COMPUTER ARCHITECTURE – The 5-Unit Structure
The Digital Computer. Definitions.
Definition #1:
A digital computer is a system intended to automate computations on discrete information in accordance with given algorithms.
Definition #2:
A digital computer is an union between:
a set of physical equipment: the hardware component,
a set of micro-programs: the firmware component,
a set of programs representing the software component, allowing processing by means of arithmetical and logical operations of the discrete information at very high speed in accordance with given algorithms.
5
COMPUTER ARCHITECTURE – The 5-Unit Structure
The Digital Computer. Definitions.
Definition #1:
A digital computer is a system intended to automate computations on discrete information in accordance with given algorithms.
Definition #2:
A digital computer is an union between:
a set of physical equipment: the hardware component,
a set of micro-programs: the firmware component,
a set of programs representing the software component, allowing processing by means of arithmetical and logical operations of the discrete information at very high speed in accordance with given algorithms.
Definition #3:
A digital computer is a finite automaton, that is a finite state system, capable of processing at a very high speed discrete information, in accordance with given algorithms.
6
COMPUTER ARCHITECTURE – The 5-Unit Structure
The Digital Computer. Features.
Common features of digital computers (from def.):
– The discrete nature of information;
– The computation process is totally automated;
– The processing is carried out according to given algorithms;
– The speed of processing is very high;
– The nature of processing is arithmetical and logical.
7
COMPUTER ARCHITECTURE – The 5-Unit Structure
Computing Systems Study
3 levels:
1. Computer Architecture;
2. Computer Organization;
3. Computer Implementation.
8
COMPUTER ARCHITECTURE – The 5-Unit Structure
Computer Architecture
Refers to attributes of a system visible to a programmer, that have a direct impact on the logical execution of a program.
Deals with the functional behavior of a computer system as seen by a computer programmer:
– the nature of data types,
– range of realized operations,
– memory organization,
– the set of registers that are accessible to the programmer,
– the instruction set and format,
– addressing techniques,
– I/O mechanisms.
9
COMPUTER ARCHITECTURE – The 5-Unit Structure
Computer Organization
Refers to the operational units and their interconnections that realize the architectural specifications;
Organizational attributes: hardware details transparent to the programmer, such as:
– control signals,
– detailed structure of functional blocks,
– interfaces between the computer and peripherals,
– memory technology,
– extension techniques,
– clock frequency, etc.
10
COMPUTER ARCHITECTURE – The 5-Unit Structure
Computer Implementation
The actual hardware, actual physical structure, including:
– logical design techniques,
– board layouts,
– physical interconnections,
– power supply,
– testing methods,
– interference between signals,
– mechanical design, etc.
11
COMPUTER ARCHITECTURE – The 5-Unit Structure
Arch. vs. Org. vs. Impl.
Distinction between architecture, organization and implementation is important for any computer specialist;
Many computer manufacturers offer a family of computer models:
– with the same architecture,
– but with different organizations,
=> different prices and performance characteristics.
Even if architecture remains unchanged, the available technology will determine a certain implementation;
All implementations must execute the same programs and derive the same results;
Microcomputers: changes in technology influence the organization, which in turn allows a more powerful architecture.
12
COMPUTER ARCHITECTURE – The 5-Unit Structure
The Stored Program Concept
The model on which present-day computers are based on;
Originated in a scientific paper: – John von Neumann, – US, – June 1945, – the essential lines to build a digital computer.
Derived from: the principle of stored program control;
Corresponding structure: stored program machine (stored program computer);
The stored program concept: the machine language program is stored in the computer along with pertaining data; the computer is able to manipulate the program as if it were data.
13
COMPUTER ARCHITECTURE – The 5-Unit Structure
The Stored Program Concept
The essence of stored program computer: representation of algorithms corresponding to the problem to be solved by a flowchart comprising two types of operators:
– Processing operators;
– Sequencing operators.
Any problem must be “described” to the computer as a sequence of operations executed by the computer;
The machine expects a program, that is a set of instructions, which tells it what to do from one moment to the next moment;
The processing operators specify the method of changing/ transforming the input data, whilst the sequencing operators are decoding the succession of operation execution;
There can be derived several schemes to implement this principle, but the most widely accepted is the model proposed by John Von Neumann in 1945.
14
COMPUTER ARCHITECTURE – The 5-Unit Structure
The “von Neumann” Principles
Basic elements for definition of the Von Neumann’s model of digital computers;
Scope: to simplify design and implementation of a computer;
Five principles;
Result: von Neumann Model.
15
COMPUTER ARCHITECTURE – The 5-Unit Structure
Principle #1
The information within a digital computer is binary coded, which means that it is represented with binary digits, named bits (0 and 1).
The term bit is an abbreviation for binary digit.
- n bits: one word:
n=8 bits => byte;
n=16 bits => half-word (2 bytes);
n=32 bits => word (4 bytes);
n=64 bits => double-word (8 bytes).
- A word may represent a command (instruction) or a datum (pl. data);
- There are defined two kinds of words: - Datum words: Data;
- Command words : Instructions.
16
COMPUTER ARCHITECTURE – The 5-Unit Structure
Principle #2
The distinction between data and instructions is given by the utilization context (the way of words utilization) - and not by the coding method (coding rule).
Considering a binary combination on 8 bits - 10011001:
– it can be interpreted as a numeric datum or an instruction;
– inside the computer the code is the same, both for the data and for commands;
– it is the task of the user, by the way of manipulating the information, to ensure a proper distinction.
17
COMPUTER ARCHITECTURE – The 5-Unit Structure
Principle #3
The words are placed in memory locations;
To every memory location is being assigned a specific number, called address;
Every data word or instruction word is located/stored in memory at a certain address, so that the address is a pointer to that word;
Two operations:
1. Read;
2. Write.
18
COMPUTER ARCHITECTURE – The 5-Unit Structure
Principle #3
Read: extracts a word from the memory;
Since it is a non-destructive operation, it is obtained a copy of the word located in the memory at the specified address;
The content of the location itself remains unaltered.
19
0 1 …… (n-1)
0
1
… …
k word
… …
2m-1
word copy
COMPUTER ARCHITECTURE – The 5-Unit Structure
Principle #3
Write implies insertion of a new word in the memory at the addressed location (k):
20
0 1 …… (n-1)
0
1
… …
k new word
… …
2m-1
new word
COMPUTER ARCHITECTURE – The 5-Unit Structure
Principle #4
The running algorithm is represented by means of a sequence of command words (instructions).
In general, any instruction is formed of two major fields (zones):
1. the Operation Code (OPCODE);
2. the Address.
OPCODE: also called the function of the instruction. (addition, subtraction, multiplication, complementation, division etc.)
21
0 1……….(L-1) 0 1……….(k-1) 0 1………(k-1)
OPCODE ADDRESS1 …… ADDRESSp
operation code
2 ᶫ operations
addresses of the operands/result
2 ᴷ different addresses => address space
COMPUTER ARCHITECTURE – The 5-Unit Structure
Principle #5
The data processing performed by the processor is determined by the sequential instruction execution constituting the program for the implemented algorithm.
Computation program: set of instructions;
A computer can accept a finite set of possible programs;
This range depends on the computer capabilities;
The set of accepted programs by a computer: the class of realizable functions of a digital computer;
Conclusion: The main feature outlined from these principles is the procedurality in solving any problem submitted to a digital computer, materialized in an algorithm and a program;
Procedurality: any problem must be presented to the computer as a sequence of operations, i.e. a sequence of instructions.
22
COMPUTER ARCHITECTURE – The 5-Unit Structure
The “von Neumann” Model
In conformity with the von Neumann principles;
A digital computer: a system formed out from several sub-systems or units;
A digital computer MUST consist in 5 units:
– an input medium: by means of which an essentially unlimited number of operands (data items) or instructions may be entered;
– a storing medium: from which operands (data) and instructions may be obtained and into which the results may be entered;
– a processing section: capable of carrying out arithmetic or logical operations on any operands taken from the storage;
– an output medium: by means of which an unlimited number of results may be delivered to the user;
– a control section: capable of interpreting instructions extracted from the memory and capable of choosing between alternative computer results.
23
COMPUTER ARCHITECTURE – The 5-Unit Structure
The fundamental structure
The 5-unit structure:
1. Input Unit (IU);
2. Arithmetic and Logic Unit (ALU);
3. Memory Unit (MU);
4. Output Unit (OU);
5. Control Unit (CU).
Virtually, all computers built since that time have been used this organization.
24
COMPUTER ARCHITECTURE – The 5-Unit Structure
The fundamental structure
25
Flux de date
Comenzi sau linii de control
Informatii de stare sau linii de stare
Flux de date alternativ
Flux de instructiuni
CPU
Date de
intrare si
programe
Unitatea
Logico-
Aritmeticã
(ALU)
Unitatea de
Intrare
(UI)
Unitatea de
Iesire
(UO)
Unitatea de
Control
(UC)
Unitatea de
Memorie
(UM)
Date de iesire
sau rezultate
DMA DMA
DateInstructiuni
Data flow
Alternative Data Flow
Instructions Flow
Control Line
Status Line
= ALU + CU
Control
Unit
(CU)
Input
Unit
(IU)
Output
Unit
(OU)
Arithmetic
Logic Unit
(ALU)
Memory
Unit
(MU)
Instructions
Input Data
&
Programs
Output Data
&
Results
COMPUTER ARCHITECTURE – The 5-Unit Structure
Functioning
26
Data and programs are introduced inside the computer through the Input Unit (IU);
Initially: they were transferred in the MU directly through ALU;
BUT: data transfer in the MU is a slow process => slows down CPU’s (ALU+UC) activity;
Input Unit
(UI)
Arithmetic Logic Unit
(ALU)
Memory Unit
(MU)
Input Data
&
Programs
CPU
COMPUTER ARCHITECTURE – The 5-Unit Structure
Functioning
27
Today: IU-MU transfer via DMA (Direct Memory Access):
Input Data
&
Programs
Output Data
&
Results
Unitatea de
Memorie
(UM)
Unitatea de
Control
(UC)
Unitatea de
Intrare
(UI)
Unitatea de
Ieșire
(UO)
DMA
Control
Unit
(CU)
Input
Unit
(IU)
Output
Unit
(OU)
Memory
Unit
(MU)
COMPUTER ARCHITECTURE – The 5-Unit Structure
Functioning
28
Data and programs are introduced inside the computer through the IU;
IU informs DMA about the presence of data/programs in the IU;
DMA informs UC about the presence of data/programs in the IU;
UC sends a command to the DMA to start the transfer of data/programs;
DMA forwards the command to the IU;
IU begins the transfer to the DMA;
DMA transfers the data/programs to the MU;
Same happens for the MU-OU transfer via DMA.
COMPUTER ARCHITECTURE – The 5-Unit Structure
Functioning
29
Flux de date
Comenzi sau linii de control
Informatii de stare sau linii de stare
Flux de date alternativ
Flux de instructiuni
CPU
Date de
intrare si
programe
Unitatea
Logico-
Aritmeticã
(ALU)
Unitatea de
Intrare
(UI)
Unitatea de
Iesire
(UO)
Unitatea de
Control
(UC)
Unitatea de
Memorie
(UM)
Date de iesire
sau rezultate
DMA DMA
DateInstructiuni
Data flow
Alternative Data Flow
Instructions Flow
Control Line
Status Line
= ALU + CU
Control
Unit
(CU)
Input
Unit
(IU)
Output
Unit
(OU)
Arithmetic
Logic Unit
(ALU)
Memory
Unit
(MU)
Instructions
Input Data
&
Programs
Output Data
&
Results
COMPUTER ARCHITECTURE – The 5-Unit Structure
Functioning
30
MU informs CU that the transfer in the MU has been completed;
CU sends command to the MU to forward the instruction to be executed;
MU transfers the instruction to the CU;
CU interprets the instruction (OPCODE + ADDRESSES) &:
– Commands the MU that the operands localized at the ADDRESSES specified in the body of the instruction to be transferred to ALU;
– UM transfers the operands to ALU;
– UC commands ALU to execute the operation specified in the OPCODE using the operands received from MU;
– The result of the operation is stored in ALU (Accumulator).
COMPUTER ARCHITECTURE – The 5-Unit Structure
Functioning
31
The result in ALU may:
– stay in ALU in order to be used for executing a new instruction, or;
– transferred and stored in MU.
The result stored in MU can be displayed by the OU by
means of DMA;
The data/results transfer from MU to OU is performed in the same manner as the IU-MU transfer.
COMPUTER ARCHITECTURE – The 5-Unit Structure
Input Unit (IU)
32
CPU
Date de
intrare si
programe
Unitatea
Logico-
Aritmeticã
(ALU)
Unitatea de
Intrare
(UI)
Unitatea de
Iesire
(UO)
Unitatea de
Control
(UC)
Unitatea de
Memorie
(UM)
Date de iesire
sau rezultate
DMA DMA
DateInstructiuni
= ALU + CU
Control
Unit
(CU)
Input
Unit
(IU)
Output
Unit
(OU)
Arithmetic
Logic Unit
(ALU)
Memory
Unit
(MU)
Instructions
Input Data
&
Programs
Output Data
&
Results
COMPUTER ARCHITECTURE – The 5-Unit Structure
Input Unit (IU)
Connects the computer and the outer environment;
Allows introducing information inside the computer;
Two ways of functioning:
– Direct: by means of input devices: keyboard, mouse, scanner;
easier;
slower speed.
– Indirect: using an intermediate medium in order to read
information e.g. card reader, microfilm reader, paper tape reader etc.
proccess: human operator -> document -> intermediate medium -> reader -> computer;
rapid;
more time consuming to prepare information.
33
COMPUTER ARCHITECTURE – The 5-Unit Structure
Arithmetic Logic Unit (ALU)
34
CPU
Date de
intrare si
programe
Unitatea
Logico-
Aritmeticã
(ALU)
Unitatea de
Intrare
(UI)
Unitatea de
Iesire
(UO)
Unitatea de
Control
(UC)
Unitatea de
Memorie
(UM)
Date de iesire
sau rezultate
DMA DMA
DateInstructiuni
= ALU + CU
Control
Unit
(CU)
Input
Unit
(IU)
Output
Unit
(OU)
Arithmetic
Logic Unit
(ALU)
Memory
Unit
(MU)
Instructions
Input Data
&
Programs
Output Data
&
Results
COMPUTER ARCHITECTURE – The 5-Unit Structure
Component of the Central Processing Unit (CPU);
The only unit to generate new information;
Carries out arithmetic and logic operations;
High speed;
The most performant and productive unit;
ALU is the most rapid, the most performant and
the most productive unit in the computer.
Performance criterium: # of addition operations per second.
Arithmetic Logic Unit (ALU)
35
COMPUTER ARCHITECTURE – The 5-Unit Structure
Memory Unit (MU)
36
CPU
Date de
intrare si
programe
Unitatea
Logico-
Aritmeticã
(ALU)
Unitatea de
Intrare
(UI)
Unitatea de
Iesire
(UO)
Unitatea de
Control
(UC)
Unitatea de
Memorie
(UM)
Date de iesire
sau rezultate
DMA DMA
DateInstructiuni
= ALU + CU
Control
Unit
(CU)
Input
Unit
(IU)
Output
Unit
(OU)
Arithmetic
Logic Unit
(ALU)
Memory
Unit
(MU)
Instructions
Input Data
&
Programs
Output Data
&
Results
COMPUTER ARCHITECTURE – The 5-Unit Structure
Stores data and programs;
Key characteristics:
1) Performance: access time, cycle time, transfer rates, etc;
2) Physical type: semiconductor, magnetic, optical, magneto-
optical, etc;
3) Unit of transfer: word, byte, block;
4) Capacity: word size, number of words;
5) Location: internal(main), external(secondary);
6) Access mode: sequential, direct, random, associative;
7) Organization;
8) Physical characteristics: volatile/nonvolatile, erasable/non
erasable, etc.
Memory Unit (MU)
37
COMPUTER ARCHITECTURE – The 5-Unit Structure
An optimal structure of memory would have the highest possible capacity and the lowest access time;
3 basic functions:
1. Write;
2. Store;
3. Read.
No processing role: does not modify information;
Characteristics: – Capacity: volume of information that can be stored (bits, bytes
or words);
Units: kilo(210), mega(220), giga(230), tera(240).
– Access Time: is the interval between the instant when a command of reading is given and the instant when the data is available;
Access time gives the speed of operation of the memory.
Memory Unit (MU)
38
COMPUTER ARCHITECTURE – The 5-Unit Structure
Memory is organized as a hierarchical structure being layered in accordance to the capacity and speed;
The major levels in the hierarchy are:
1. Main Memory (Primary Memory, Internal);
2. Secondary Memory (External).
These levels present sharp differences in:
– technology,
– speed,
– capacity,
– management,
– sublevels.
Memory Unit (MU)
39
COMPUTER ARCHITECTURE – The 5-Unit Structure
Internal memory;
Large volumes (high capacity);
High rates of accessing the data (nanoseconds );
2 levels:
1. Super-Operative Memory (SOM);
2. Operative Memory (OM).
Main Memory (MM)
40
COMPUTER ARCHITECTURE – The 5-Unit Structure
The closest to the CPU;
Small capacity;
Very small access time (units or tens of nanoseconds );
Storing: – current instructions in execution,
– intermediate results, and,
– the data involved in the current execution of the program.
The main function: the matching of the speeds of operation of CPU and the Operative Memory;
Expensive resource;
A.k.a. CACHE Memory;
Control of operation through specific hardware mechanisms transparent to the user;
At present: CPUs incorporate a part of this memory.
Super-Operative Memory (SOM)
41
COMPUTER ARCHITECTURE – The 5-Unit Structure
Contains the program in execution and the corresponding
data;
The capacity of OM is larger than that of SOM;
The access time is worse;
Nowadays: the OM capacity is measured in Megabytes;
Operation of OM is based on Random Access technique:
Random Access Technique: the time to get access to
any location is identical, regardless its address;
Realized using semiconductor technologies (including RAM,
DRAM, SRAM memories).
Operative Memory (OM)
42
COMPUTER ARCHITECTURE – The 5-Unit Structure
External memory;
Central Unit = CPU + MM;
SM: external storage devices (HDD, FDD, CD-ROM, DVD-ROM, etc)
Greater capacities than MM;
Greater access times than MM (micro to miliseconds);
Smaller costs per bit than MM;
Stores large sets of data, measured in MB, GB, TB;
If a program is stored in SM in order to be executed it must firstly be transferred into the MM;
Transfer rate is the rate at which the data can be transferred into or from a memory unit.
Secondary Memory (SM)
43
COMPUTER ARCHITECTURE – The 5-Unit Structure
The fundamental structure (2)
44
Date de
intrare si
programe
Unitatea
Logico-
Aritmeticã
(ALU)
Unitatea de
Intrare
(UI)
Unitatea de
Iesire
(UO)
Unitatea de
Control
(UC)
Memorie
Superoperativa
(MSO)
CPU
Date de iesire
sau rezultate
DMA DMA
DateInstructiuni
Memorie
Operativa
(MO)
Memorie
Secundara
(MS)
Date
Date
Unitatea Centrala
MP
Control
Unit
(CU)
Input
Unit
(IU)
Output
Unit
(IU)
Arithmetic
Logic Unit
(ALU)
SOM
OM
SM
Flux de date
Comenzi sau linii de control
Informatii de stare sau linii de stare
Flux de date alternativ
Flux de instructiuni
Data flow
Alternative Data Flow
Instructions Flow
Control Line
Status Line
Input Data
&
Programs
Output Data
&
Results Instructions
Central Unit
MM
COMPUTER ARCHITECTURE – The 5-Unit Structure
Control Unit (CU)
45
CPU
Date de
intrare si
programe
Unitatea
Logico-
Aritmeticã
(ALU)
Unitatea de
Intrare
(UI)
Unitatea de
Iesire
(UO)
Unitatea de
Control
(UC)
Unitatea de
Memorie
(UM)
Date de iesire
sau rezultate
DMA DMA
DateInstructiuni
= ALU + CU
Control
Unit
(CU)
Input
Unit
(IU)
Output
Unit
(OU)
Arithmetic
Logic Unit
(ALU)
Memory
Unit
(MU)
Instructions
Input Data
&
Programs
Output Data
&
Results
COMPUTER ARCHITECTURE – The 5-Unit Structure
Computer’s brain;
Role:
– managing,
– monitoring,
– supervising the operation of all units from a digital computer.
CPU component;
Ensures the complete automation of the computing process;
Contains mainly registers, counters, frequency dividers, controllers, decoders etc.
Two classes:
– Hardwired;
– Microprogrammed.
Control Unit (CU)
46
COMPUTER ARCHITECTURE – The 5-Unit Structure
Implements the fundamental mechanism of instruction execution:
reads the current instruction from the memory (OM or
SOM);
decodes it (interprets it) in order to decide the function to be
executed and to activate the corresponding control signals
and ultimately,
executes it, yielding the result.
Control Unit (CU)
47
COMPUTER ARCHITECTURE – The 5-Unit Structure
Output Unit (OU)
48
CPU
Date de
intrare si
programe
Unitatea
Logico-
Aritmeticã
(ALU)
Unitatea de
Intrare
(UI)
Unitatea de
Iesire
(UO)
Unitatea de
Control
(UC)
Unitatea de
Memorie
(UM)
Date de iesire
sau rezultate
DMA DMA
DateInstructiuni
= ALU + CU
Control
Unit
(CU)
Input
Unit
(IU)
Output
Unit
(OU)
Arithmetic
Logic Unit
(ALU)
Memory
Unit
(MU)
Instructions
Input Data
&
Programs
Output Data
&
Results
COMPUTER ARCHITECTURE – The 5-Unit Structure
Ensures communication between a digital computer and the outside world;
Two main modes of operation:
1. Direct: video monitors, printers etc.
2. Indirect: card punchers, tape punchers etc.
IU + OU = I/O Peripheral Equipment (I/O Units);
Major I/O function: remote communication - enabling
specialized I/O communication devices ( MODEMS,
communication cards, bridges, routers etc.)
Output Unit (OU)
49
COMPUTER ARCHITECTURE – The 5-Unit Structure
Program: stored in memory;
Program: set of instructions;
Instructions are written in code-machine language => machine language instructions, hence the program is called machine language program;
Acc. to von Neumann principle, the program is sequentially executed by the CPU (instruction by instruction).
Definition:
The set of operations to be performed in order to execute one instruction is called instruction cycle.
Instruction Cycle
50
COMPUTER ARCHITECTURE – The 5-Unit Structure
Phases, in executing an instruction:
– FETCH: Reading the instruction from the MU and
transferring it in the CPU;
– EXECUTE: Executing the instruction and generating the
result.
The CPU must be informed about where the operands are stored and where to store the result;
The CPU must also know where to find the next instruction;
Phases repeat while running a program;
A sequence FETCH-EXECUTE: the instruction cycle;
By this simple sequence of operation at infinitum, a CPU can execute programs of any complexity.
Instruction Cycle
51
COMPUTER ARCHITECTURE – The 5-Unit Structure
Instruction Cycle
52
Instruction Cycle Instruction Cycle
Time
Instruction Cycle
FETCH EXECUTE
FETCH EXECUTE
FETCH EXECUTE
COMPUTER ARCHITECTURE – The 5-Unit Structure
Phases:
1. The CPU reads from the MU, at the address specified by the Program Counter (PC), the instruction to be executed and stores it in a register from the CU, called Instruction Register (IR);
2. In CU, the Instruction is divided into its two major fields,
OPCODE and ADDRESS, and stored accordingly into the Function Register (FR) and Address Register (AR);
Instruction:
3. CU decodes the OPCODE, i.e. the content of the Function Register (FR) => decoding the OPCODE, or interpreting the OPCODE.
FETCH
53
0 1…………..(L-1) 0 1…………...(n-1)
OPCODE ADDRESS
COMPUTER ARCHITECTURE – The 5-Unit Structure
Phases:
5. Using the information from the Address Register (AR), the Control Unit must determine the effective addresses of the operands.
6. The CPU reads the memory again to extract the necessary operands; this phase is known to be FETCH DATA.
The operand is transferred in the ALU.
Sometimes, operands are placed inside the CPU, in the register file of the ALU, constituting the local memory of the CPU; in such cases a new Read Memory operation is not required, the data (operands) are much faster supplied directly from the local memory of the CPU.
7. The CPU effectively realizes the operation specified by the OPCODE, by processing the operands according to the given
operation in the instruction.
EXECUTE
54
COMPUTER ARCHITECTURE – The 5-Unit Structure
Phases:
5. The result can be stored in the memory;
To realize this, a Write Cycle in the memory is started, by which the result of processing is stored in the memory at an address determined at step 5.
Most frequently this step is missing from the instruction cycle, as the result is saved inside the CPU’s registers, for instance in a dedicated register, the Accumulator, having in view further processing.
EXECUTE
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COMPUTER ARCHITECTURE – The 5-Unit Structure
Instruction Cycle
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Fetch
Instruction
Store Instruction
in FR and AR
Decode
OPCODE
Generate Address
of the next
instruction
Calculate operand(s)
address (es)
Fetch Data
( operand )
Store the result
Execute operation
1
2
3
4
5
6
7
8
Fetch
Phase
Execute
Phase
Instruction
Cycle
COMPUTER ARCHITECTURE – The 5-Unit Structure
Instruction Cycle
57
Some of the steps from an Instruction Cycle may be absent in certain instructions;
Instructions without operands: steps (5), (6) are not required;
JUMP instructions: steps (4), (5), (8) are skipped;
Comparison instructions the result is not stored, as only the flags (condition bits) from ALU are updated;
For instructions defining multiple operands, the steps (5) and (6) are repeated several times until all operands are fetched in ALU;
A digital computer must go through thousands, millions or even billions of Instruction Cycles to fully process a single program;
Always the FETCH phase is unique, whereas EXECUTE phase presents manifold aspects, depending on the concrete instruction to be executed.
COMPUTER ARCHITECTURE – The 5-Unit Structure
Instruction Cycle
58
The time required for running an Instruction Cycle depends on the machine cycle, defined by the time clock cycle;
In the computer world speeds are rated in Megahertz (MHZ) or Gigahertz (GHZ).
Each MHZ represents one million clock pulses per second, while each GHZ represents one billion clock pulses per second.
Currently there are manufactured microcomputers running at a speed over 1 GHZ.
Therefore, at present the instruction cycles are measured in microseconds and nanoseconds (10 - 9 sec).